Synopsys has expanded its presence across several advanced engineering markets through a series of initiatives tied to AI infrastructure, aerospace systems, semiconductor verification, and digital simulation platforms.
The company is supporting NASA Artemis-related programs while expanding collaboration with major semiconductor and compute companies including TSMC, NVIDIA, Arm, AMD, and Amazon Web Services
NASA-related work includes lunar communications infrastructure and spacesuit electrostatic safety analysis, while industry initiatives span AI-assisted chip design, hardware-assisted verification, digital twins, and advanced packaging simulation.
Recent product launches and partnerships suggest Synopsys is growing beyond its traditional role as an electronic design automation company. It is becoming a broader engineering infrastructure provider focused on simulation, verification, and system-level development. This shift reflects rising demand for tools that can manage the growing complexity of AI datacenters, robotics, software-defined systems, automotive platforms, aerospace technologies, and advanced semiconductor designs.
Synopsys’ role in Artemis mission
NASA selected Synopsys and Electro Magnetic Applications (EMA) to support Artemis lunar mission preparation through engineering simulation and digital validation systems. The collaboration focuses on analyzing electrostatic charging risks affecting Artemis spacesuits exposed to lunar plasma conditions and interactions with lunar regolith. NASA is studying how these conditions could create electrostatic discharge events capable of damaging mission-critical electronics used for communications and life-support systems.
The work incorporates several Synopsys technologies, including Ansys Charge Plus, HFSS electromagnetic simulation, RF Channel Modeler, and digital mission engineering systems. These tools are being used to model charging behavior, plasma interactions, and communications performance in simulated lunar conditions before hardware deployment. The simulations are paired with physical validation activities conducted at EMA’s Space Environment and Radiation Effects Laboratory, which can replicate key aspects of the lunar plasma environment.
NASA’s Glenn Research Center is also using Synopsys tools to simulate lunar radio-frequency coverage and identify terrain-driven communications shadow zones that could disrupt surface connectivity. Using digital lunar terrain environments developed with Cesium, engineers are evaluating how craters, rock formations, and lunar topography could affect future Moon-based communications infrastructure. The broader significance of the project is that Synopsys is becoming embedded in aerospace engineering workflows where simulation increasingly substitutes for expensive or operationally impossible real-world testing.
From simulation to software-defined physical AI systems
The same engineering infrastructure supporting NASA Artemis missions is increasingly being applied to software-defined vehicles, robotics systems, autonomous platforms, and AI datacenters. Synopsys’ Electronics Digital Twin (eDT) Platform was launched to support simulation-based system development using virtualized hardware environments, cloud-native validation systems, and collaborative software testing workflows.
The eDT Platform allows automotive manufacturers to complete up to 90% of software validation before hardware production. The platform includes support for virtual electronic control units, system-level software testing, and integration into continuous testing workflows designed to reduce prototyping costs and shorten development cycles. Supporting ecosystem participants include Volvo Cars, AWS, and Arm.
Synopsys also expanded collaboration with NVIDIA around AI-assisted chip design, robotics simulation, digital twins, and GPU-accelerated multiphysics workloads. During NVIDIA GTC 2026, several companies highlighted measurable reductions in engineering simulation times using GPU-accelerated Synopsys workflows. Honda reported 34-times faster computational fluid dynamics simulations, Applied Materials reported up to 30-times faster quantum chemistry simulations, and Astera Labs reported 3.5-times faster circuit simulations using AWS GPU infrastructure. These developments indicate that engineering workflows are increasingly converging with AI compute infrastructure and simulation-driven development environments.
Scaling chip design for AI and high performance computing
Synopsys expanded collaboration with TSMC across advanced semiconductor manufacturing nodes and packaging technologies tied to AI and high-performance computing infrastructure. The partnership includes support for TSMC’s N2P and A14 process technologies, 224G connectivity IP, UCIe 64G chiplet interconnects, AI-assisted EDA workflows, and CoWoS and 3DFabric packaging integration.
The developments are aimed at supporting increasingly complex multi-die AI systems that require higher bandwidth, improved thermal management, and more advanced interconnect architectures.
Synopsys said its 3DIC Compiler platform supports large-scale multi-die systems with integrated thermal, power, and signal integrity analysis, while expanding support for co-packaged optics architectures needed for faster and more efficient AI datacenter connectivity.
The company also introduced updated HAPS-200, ZeBu-200, and ZeBu Server 5 verification systems to address growing AI chip complexity through larger FPGA emulation capacity, coherency testing, mixed-signal modeling, and software-defined pre-silicon validation. Synopsys added that AI model sizes and bandwidth demands are outpacing conventional semiconductor validation workflows and noted its collaboration with Arm on the Arm AGI CPU platform for AI datacenters and hyperscale infrastructure.
Synopsys: Patenting Activity
Synopsys’ global patent filings expanded sharply between 2019 and 2021, peaking at 322 filings in 2020. The surge coincided with accelerated industry investment in AI-enabled electronic design automation (EDA), advanced semiconductor IP, and next-generation 5nm system-on-chip development.
In 2020, Synopsys highlighted Samsung’s adoption of its machine learning-driven IC Compiler II platform for 5nm mobile SoC production, highlighting the company’s push into AI-assisted chip design and optimization technologies. The company also expanded its high-bandwidth memory and advanced packaging portfolio in 2020, including the launch of silicon-proven HBM2E PHY IP designed for high-performance computing, AI, and networking workloads.
The elevated patent activity also aligned with strong growth in Synopsys’ Semiconductor & System Design business, which accounted for more than 90% of fiscal 2020 revenue.
Synopsys: Top Technology Areas
Synopsys’ patent portfolio from 2015 to 2025 is heavily concentrated in electric digital data processing (G06F), which accounts for more than half of total filings. Static stores (G11C) and computing arrangements based on specific computational models (G06N) represent the next largest categories, underscoring the company’s strong focus on semiconductor design software, memory architectures, and AI-enabled computing technologies. The prominence of these classifications reflects Synopsys’ position at the center of electronic design automation (EDA), high-performance computing, and advanced chip development.
Beyond its core computing and semiconductor exposure, the portfolio spans a broad range of enabling technologies tied to chip manufacturing and data infrastructure. Categories including photomechanical production of patterned surfaces (G03F), semiconductor devices (H01L), and electronic memory devices (H10B) highlight Synopsys’ involvement in lithography, advanced process technologies, and memory integration. Meanwhile, filings related to pulse techniques (H03K), digital information transmission (H04L), and electrical measurement systems (G01R) indicate continued investment in signal integrity, communications infrastructure, and chip testing technologies, reinforcing the company’s strategic alignment with AI workloads, advanced packaging, and next-generation semiconductor systems.
Synopsys’ patents reflect AI-driven chip design and semiconductor infrastructure expansion
Synopsys’ recent patents highlight its focus on AI-driven EDA, chip testing, hardware security, and advanced memory systems. We looked at its patents targeting key challenges in next-generation chip design, including defect localization, low-power memory integration, and hardware-level security. Overall, the portfolio reflects trends in high-performance computing, advanced process nodes, and more efficient SoC architectures.
Scan chain design for better defect detection in integrated circuits
The problem
Modern chips use scan chains to find manufacturing defects like stuck connections, open circuits, and shorts. A scan chain links thousands of small test points in the chip so test signals can move through it during production testing. As chips become more complex, it gets harder to pinpoint exactly where a defect is. Traditional designs often group related test points together, but this can make results less clear because nearby points can behave similarly during testing. This makes debugging harder, slows down testing, and reduces the efficiency of automated test systems used in chip development.
How the patent solves itU.S. Patent No. 12,282,063 introduces a system and method for forming scan chains that improve defect localization by intelligently arranging scan cells within the chain. The approach analyzes logical relationships between scan cells and positions related cells outside an “extended neighborhood” of one another inside the scan chain. The extended neighborhood includes downstream scan cells and adjacent upstream scan cells that could otherwise interfere with accurate fault isolation. By separating logically coupled scan cells, the system improves the ability to pinpoint defects during scan testing.
The patent also describes additional optimization techniques, including the insertion of inverters or multiplexers between selected scan cells to further improve chain resolution and diagnostic accuracy. A scoring system evaluates candidate scan chain configurations based on factors such as defect localization capability, wire length, and power consumption, allowing the processor to select an optimized scan chain architecture automatically.
Why it matters
As chips continue scaling into increasingly dense and heterogeneous architectures, efficient fault diagnosis becomes critical for manufacturing yield, reliability, and time-to-market. Improving scan chain resolution enables engineers to isolate defects faster and with greater precision, reducing debugging overhead during both silicon bring-up and high-volume production.
The approach also supports more advanced ATPG workflows and can improve overall test efficiency without requiring major changes to existing scan-based testing infrastructure. By balancing diagnostic accuracy with practical constraints such as routing complexity and power usage, the system provides a scalable method for improving semiconductor test quality in modern integrated circuit designs.
The patent, titled “Scan chain formation for improving chain resolution,” was filed on December 6, 2023, and granted on April 22, 2025. The listed inventors are Emil Gizdarski and Fadi Maamari. Legal representation was provided by Patterson + Sheridan.
One-time programmable memory for low-power, high-density chips
The problem
One-time programmable (OTP) memory is used in chips to permanently store things like device IDs, security keys, calibration data, and RFID information. Anti-fuse OTP is popular because it fits well with standard chip manufacturing and uses very small memory cells.
But as devices get smaller and use less power, traditional designs face problems. They often need high voltage to program the memory, which requires extra circuitry that takes up space and increases complexity. This makes it harder to use in small devices like phones, wearables, and IoT products. There is also a challenge in making sure only the correct memory cells are permanently programmed without affecting nearby cells.
How the patent solves it
U.S. Patent No. 10,777,288 introduces a one-time programmable memory architecture that integrates an inhibit device directly into the OTP bit cell structure. The design uses anti-fuse FinFETs together with dedicated access FinFETs arranged in separate regions of the integrated circuit. During programming operations, the access FinFET selectively applies either a program-enable voltage or a program-inhibit voltage to the anti-fuse device. This allows the system to precisely control which memory elements are permanently programmed while preventing unintended programming in neighboring cells.
The architecture also improves area efficiency by organizing the anti-fuse and access devices in a manner compatible with advanced FinFET manufacturing processes. By integrating the inhibit functionality directly into the memory cell design, the system reduces reliance on large external programming support circuitry while maintaining reliable programming behavior.
Why it matters
As modern electronics continue shifting toward smaller, lower-power, and highly integrated devices, efficient non-volatile memory becomes increasingly important. OTP memories are widely used for secure device configuration, hardware identification, and embedded system personalization, particularly in applications where data must remain permanent and tamper resistant.
This invention supports higher-density OTP memory arrays while helping reduce chip area and power overhead associated with high-voltage programming circuitry. The improved programming control also enhances reliability, which is critical for consumer electronics, industrial systems, IoT devices, and secure semiconductor applications. By aligning OTP memory architecture with FinFET manufacturing technologies, the approach enables more scalable and efficient integration into advanced semiconductor processes.
The patent, titled “One time programmable (OTP) bit cell with integrated inhibit device,” was filed on August 7, 2019, and granted on September 15, 2020. The listed inventor is Wlodek Kurjanowicz. Legal representation was provided by Fenwick & West.
Side-channel resistant public key cryptography for hardware encryption
The problem
Public key cryptography is essential for encrypted communications, authentication, and digital signatures across cloud, mobile, and embedded systems. However, while cryptographic algorithms may be mathematically secure, hardware implementations can still be vulnerable to side-channel attacks such as differential power analysis (DPA), where attackers analyze power consumption patterns during operations to infer secret cryptographic keys.
How the patent solves it
U.S. Patent No. 12,353,570 introduces a side-channel resilient cryptographic processing method designed to obscure power-analysis signatures during public key operations. The system processes an input message while iterating through portions of a secret key and performing both real and randomized dummy operations during computation.
The architecture pre-computes multiple values from the input message and randomly selects them during cryptographic operations, including dummy calculations, to obscure power-consumption patterns and reduce vulnerability to differential power analysis (DPA). The design also supports modular exponentiation and elliptic curve cryptography (ECC) while using randomized protection modes to further strengthen resistance to side-channel attacks.
Why it matters
The architecture uses randomized pre-computed values and dummy calculations during cryptographic operations to obscure power-consumption patterns and reduce vulnerability to differential power analysis (DPA). The design also supports modular exponentiation and elliptic curve cryptography (ECC) while using randomized protection modes to strengthen resistance to side-channel attacks.
The patent, titled “Side-Channel Resilient Public Key Cryptography,” was filed on June 28, 2023, and granted on July 8, 2025. The listed inventors are Nimisha Limaye and Michael Kenneth Bowler. Legal representation was provided by Womble Bond Dickinson.
Synopsys: Top Law Firms
Synopsys relies on a concentrated network of intellectual property firms to manage its global patent portfolio, led by Fenwick & West and supported by a geographically diversified group of patent specialists, including King & Wood Mallesons, Patterson + Sheridan, Park, Vaughan, Fleming & Dowler, Patentanwaltsgesellschaft MBH, Epping – Hermann – Fischer, Haynes Beffel & Wolfeld, Weaver Austin Villeneuve & Sampson, Alston & Bird, and Lee and Li-Leaven. The broad mix of U.S., Chinese, and European legal practices reflects Synopsys’ international patent filing strategy across major semiconductor, AI, and advanced computing jurisdictions.
The geographic diversity of Synopsys’ legal representation highlights the company’s position within globally interconnected semiconductor supply chains and advanced chip design markets. The distribution of firms across multiple jurisdictions also suggests a coordinated intellectual property strategy focused on protecting AI-enabled electronic design automation (EDA), semiconductor IP, memory technologies, and high-performance computing innovations across both established and emerging technology markets.