GlobalWafers, a subsidiary of Taiwan-based Sino-American Silicon Products, received over $200 million in funding in June under the U.S. CHIPS and Science Act to boost semiconductor production. This grant is part of the larger $406 million funding initially announced in December 2024 under the Biden administration. About half of the grant secured was due to its milestone projects in Texas and Missouri in expanding U.S. silicon wafer production.
GlobalWafers Co., Ltd, founded in Taiwan in 201, is one of the world’s largest silicon wafer suppliers (third-largest as of 2023). It operates 18 production sites across 9 countries in Asia, North America, and Europe, with nearly 17% global market share. GlobalWafers America (GWA) is headquartered in Sherman, Texas, and operates a manufacturing facility in St. Peters, Missouri.
US CHIPS and Science Act overview
The CHIPS and Science Act, signed on August 9, 2022, directs $280 billion to boost U.S. semiconductor research and manufacturing. It designates $52.7 billion for manufacturing subsidies and $39 billion for chip-making incentives, while also funding research, workforce training, and technology development. Its goal is to strengthen supply chain resilience and curb foreign dominance in advanced technologies.
GlobalWafers secured part of this funding to expand U.S. silicon wafer production. The December 2024 subsidy backs construction of the nation’s first high-volume 300 mm wafer plant and a new SOI wafer facility for defense and aerospace.
(Related article: Chipping in: The US and EU Semiconductor Patent Landscape Post-CHIPS Act)
In the following sections, we will examine GlobalWafers’ patent portfolio and its alignment with the objectives of the U.S. CHIPS and Science Act.
GlobalWafers: Patenting Activity
GlobalWafers’ U.S. patenting activity reached its highest in 2020, likely reflecting R&D investments from prior years. Beginning in 2018, the company advanced projects such as its groundbreaking GaN-on-novel SOI (AlN) technology, which involves growing gallium nitride (GaN) on a silicon-on-insulator (SOI) substrate that uses aluminum nitride (AlN) instead of the conventional silicon dioxide (SiO₂). This innovation was developed in collaboration with the National Nano Device Laboratories (now Taiwan Semiconductor Research Institute) and National Chiao Tung University (NCTU).
GlobalWafers: Top Law Firms
In the U.S., GlobalWafers was primarily represented by Armstrong Teasdale LLP. They have been their legal representative for 176 patent filings, which includes one of their earliest patents in 2015. Other key law firms in GlobalWafers network are Jianq Chyun IP Group (also known as JCIPRNET) and Li & Cai IP Office, both of which are headquartered in Taiwan but have networks in the U.S.
Other notable law firms include Buchanan Ingersoll & Rooney PC, Osha Bergman Watanabe & Burton LLP, Wenderoth, Lind & Ponack, L.L.P., and Apex Juris, PLLC (primarily with lawyers Wylie R. Lynette and Tracy Heims).
GlobalWafers: Top Technology Areas
GlobalWafers’ patent fillings are highly concentrated in two technology areas: single-crystal growth (C30B) at 43.6% and semiconductor devices (H01L) at 41.8%. This dominance reflects GlobalWafers’ positioning as a critical supplier in the semiconductor value chain, particularly in producing high-quality wafers for integrated circuits and next-generation chips.
The rest of the portfolio spans supporting technologies, with grinding/polishing (B24B) and material analysis (G01N) driving wafer processing and quality control. Smaller shares, such as stone-like materials (B28D), metallic coatings (C23C), and cleaning (B08B), support process optimization and reliability.
GlobalWafers’ patented technologies
GlobalWafers’ focus technologies align well with CHIPS Act objectives, strengthening domestic semiconductor component manufacturing through advanced R&D, enabling onshore production of critical materials like 300 mm wafers and SOI wafers, and ultimately fostering U.S. innovation and supply chain autonomy.
Graded aluminum buffer layer for semiconductors
Nitride-based semiconductors are widely used in LEDs, power electronics, and wireless communication systems, but manufacturing challenges often create stress and defects where material layers meet. These defects can reduce efficiency and reliability in the final device.
U.S. Patent No. 11,705,489 describes a buffer layer structure that improves gallium nitride (GaN) semiconductors. The invention introduces a buffer made from aluminum, gallium, and sometimes indium, where the aluminum concentration is carefully controlled. This can be done gradually, by increasing and then decreasing the content smoothly, or in discrete steps.
By managing the aluminum composition, the buffer layer reduces stress and defects at the interfaces, leading to more reliable and higher-performing devices. The patent also covers fabrication methods for building these layers, making it applicable to a wide range of electronics requiring durable, efficient GaN technology.
The patent, titled “Buffer layer structure to improve GaN semiconductors,” was filed on December 19, 2018, and published on July 18, 2023. Inventors listed in the patent include Jia-Zhe Liu, Yen Lun Huang, Chih-Yuan Chuang, Che Ming Liu, Wen-Ching Hsu, and Manhsuan Lin. Legal representation was provided by Osha Bergman Watanabe & Burton LLP, with attorneys Peter Schechter, Jonathan Osha, Thomas Scherer et al. named on the application.
Thermally stable charge trapping SOI substrate
Silicon-on-insulator (SOI) technology is critical for RF (radio frequency) devices because it enables superior electrical isolation, reduced power loss, and improved signal integrity. However, formation of parasitic conduction layers at the substrate interface degrades performance.
U.S. Patent No. 10,381,261, provides a method to manufacture improved SOI wafers. The focus is on adding a special layer, called a charge trapping layer, between the base wafer (handle wafer) and the insulating layer. This layer is made from materials like polycrystalline or amorphous silicon, silicon-germanium, or similar compounds, and it helps prevent unwanted electrical charges from building up and interfering with the device’s performance.
Unlike previous methods, this new approach keeps the charge trapping effect stable even after high-temperature processing, which is common during chip manufacturing. The result is a more reliable and efficient base for building advanced RF devices, with reduced power loss, signal distortion, and better overall electrical performance.
The patent, titled “Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers,” was filed on May 21, 2018, and later published on August 13, 2019. Inventors include Igor Peidous, Jeffrey L. Libbert, Srikanth Kommu, Andrew Marquis Jones, Samuel Christopher Pratt, Horacio Josue Mendez, Leslie George Stanton, and Michelle Rene Dickinson. GlobalWafers was represented by Richard A. Schuth from Armstrong Teasdale LLP for the filing of this patent.
Non-rotational mono-crystalline silicon growth method
Mono-crystalline silicon is a single, continuous crystal structure of silicon with high purity and minimal defects. It is essential in semiconductors due to its superior electrical properties, enabling efficient performance in integrated circuits, solar cells, and electronic devices.
U.S. Patent No. 11,377,752 introduces a new method and equipment design for growing high-quality mono-crystalline silicon. Unlike traditional methods, this process keeps the silicon container (crucible) and its support base stationary relative to the heating system, improving control over temperature and crystal formation.
The method includes several stages: preparing the melted silicon, starting the crystal, expanding its width, growing the main body in three heat-controlled steps, and finally forming and removing the tail end. The heating system is divided into three separate zones placed at different heights to fine-tune temperature throughout the process. This approach helps grow more uniform, higher-quality silicon ingots while also increasing material usage and production yield, offering improvements over older methods like the Czochralski process.
The patent, titled “Mono-crystalline silicon growth method,” was filed on December 27, 2019, and was published on July 5, 2022. It lists Chun-Hung Chen, Hsing-Pang Wang, Wen-Ching Hsu, and I-Ching Li as the inventors. The law firm Li & Cai IP Office and attorneys Dennis Wang, James Long, and Zhuo Xu represented GlobalWafers for filing of this patent.
