In the rapidly evolving AI landscape, Huawei has emerged as China’s primary challenger to global AI hardware space. With efforts centered on developing its own AI processors and architectures such as Ascend 910D chip and the CloudMatrix 384 system, the company is working to close the performance gap with well-established leaders like NVIDIA and position itself as an alternative to U.S.-centric AI infrastructure.
This push comes as geopolitical tensions and US sanctions have severely restricted China’s access to advanced semiconductors, including NVIDIA’s high performance chips. (Update: On July 15, Nvidia announced that it has received approval to export certain AI chips to China after being blocked due to trade restrictions.)The U.S. chipmaker’s H100 Tensor Core GPU, powered by its Hopper architecture, delivers up to 30x performance improvement over its predecessor, the NVIDIA A100. Such gains are critical in large language model (LLM) training, autonomous driving, medical imaging, robotics, and data centers.
In this report, we explore Huawei’s AI-focused patent activity and take a closer look at the technologies underpinning its Ascend chips and CloudMatrix architecture.
Huawei’s AI Chips: Patenting Activity
Huawei’s AI chip patenting activity significantly increased from 2016, peaking in 2019. In 2017, Huawei introduced their first device-level AI chip, Kirin 970, featuring a dedicated Neural Processing Unit (NPU) in the Huawei Nova and Mate series phones. Building on this foundation, Huawei released the high-performance 7nm Kirin 980 NPU chip in 2018, followed by the mid-range Kirin 810 in 2019. That same year, Huawei expanded its AI capabilities with the launch of the Ascend 910 chip, designed for data centers and cloud AI. At the time of its release, Ascend 910 was considered the fastest AI chip, boasting 256 TFLOP/s (Terra Floating Point Operations Per Second).
Huawei’s patent filings decreased after 2019, possibly due to the National Defense Authorization Act for Fiscal Year 2019. This act included provisions that prohibited the U.S. federal government from acquiring equipment from specific Chinese suppliers, such as Huawei and ZTE, citing security concerns. In 2022, the U.S. enacted new rules to control global AI development, aiming to maintain U.S. military and technological superiority. These measures conclude a four-year effort to restrict Beijing’s access to advanced chips that could enhance its military capabilities, while reinforcing U.S. dominance in AI by closing loopholes and strengthening export controls.
Huawei’s AI Chips: Top Jurisdictions
As expected, China remains the leading jurisdiction for Huawei’s AI chip patent filings. This is followed by filings through the European Patent Office (EP) and the PCT system, reflecting Huawei’s strategic push for broader international protection and market expansion.
In contrast, the U.S., once a major venue for Huawei’s IP, placed fourth, possibly driven by export controls in the region. Jurisdictions like Germany, Japan, India, and Korea also contribute to Huawei’s diversified global filing footprint, providing targeted protections in key technical and manufacturing markets.
Huawei’s AI Chips: Top Law Firms
Backing Huawei’s international patenting efforts is a list of top-performing law firms. Leading is Shenzhen Shenjia Intellectual Property, followed by Scihead IP Law Firm and other China-based firms handling high-volume submissions. Outside China, Huawei works closely with firms like Gill Jennings & Every LLP in the UK and Pfenning, Meinig & Partner mbB in Germany.
Collectively, this legal infrastructure supports Huawei’s strategy to protect its AI chip innovations across global markets, reinforcing its long-term goal of technological self-sufficiency.
Huawei’s AI Chips: Top Technology Areas
Huawei is actively advancing its Artificial Intelligence portfolio and focusing on core areas like computing infrastructure and communication technologies. Their AI patent portfolio shows strong efforts in digital processing (G06F) , wireless systems (H04W) , and secure data transmission (H04L).
Beyond infrastructure, Huawei also partakes in research and legal protection in AI for vision (G06V, G06T, H04N), voice (G10L), and enterprise applications (G06N, G06Q)—supporting innovations in intelligent cameras, autonomous driving, and business AI systems. Their technical domain spans into image recognition, neural networks, speech processing, and AI-driven communication.
Ascend 910D: Huawei’s high-end challenger
Huawei’s Ascend 910D features advanced 3D packaging with a theoretical peak performance of 1.2 petaFLOP/s (peta floating-point operations per second), making it highly suitable for large language model (LLM) training and data center operations.
While the chip demonstrates substantial design ambitions, several technical challenges remain. These include ongoing development in areas such as memory bandwidth optimization, chip-to-chip communication efficiency, and software ecosystem support. The architecture incorporates self-developed HBM3e memory and silicon photonics interconnects, though their scalability and integration across broader system deployments are still being evaluated.
According to a WSJ report, the Ascend 910D reconstructed architecture design will be revolving around:
- Da Vinci Architecture 3.0 – adopting 3D Cube technology
- In-Memory Computing Breakthrough – self-developed HBM3e high-bandwidth memory uses 3D stacking technology
- Photonic Interconnect Technology – silicon photonics modules for ultra-fast-chip communication
CloudMatrix 384 architecture
Huawei’s CloudMatrix 384 System Architecture is a rack-scale AI supernode designed for high-throughput model training and scalable deployment. It integrates 384 Ascend 910C chips interconnected through an all-to-all optical mesh network topology, supporting increased memory capacity and bandwidth for demanding AI workloads.
The architecture consists of 16 racks, with 12 dedicated to computation and 4 to networking, connected via 6,912 high-speed optical links. Although based on an earlier generation of chips, the system delivers strong performance in language model training and large-scale computation. It achieves significant memory bandwidth and processing density, though with higher power consumption per operation—a trade-off balanced by its immediate deployability and architectural scalability.
Patents behind Huawei’s AI ecosystem
The key technologies that underpin Huawei’s AI ecosystem—namely, 3D stacked self-developed HBM3e high-bandwidth memory technology and the CloudMatrix 384 system—are backed by a collection of patents that formalize the company’s innovations in chip design, interconnect architecture, and network topology.
Cost-effective 3D memory stacking for AI chips
Huawei’s 3D stacking technology features a memory stacking method designed to improve AI chip efficiency and scalability. Detailed in EP4123695, the patent application describes a cost-effective approach for vertically stacking multiple memory chips without relying on expensive techniques like through silicon via (TSVs).
The architecture uses a layered configuration of face-down and face-up chip orientations connected via standard wire bonding. Specifically, at least five memory chips are stacked: the first layer is mounted face-down on a substrate with direct connections; the second is face-up and wire-bonded; and a fifth chip bridges the two stacks. This layered arrangement enables high-density integration while reducing manufacturing complexity and cost.
Functionally, the structure supports 64-bit processors by allocating four chips for data and one for error correction, with an optional sixth chip for redundancy. Two of these stacks can be placed side-by-side to improve mechanical stability and enhance durability during assembly.
The patent application, titled “Memory chip stacked package and electronic device” was filed on March 25, 2020, and was published on January 25, 2023. Huifang Jiao, Ran He, Wei Li, Jingxia Liu, and Tan Li are listed as the inventors and Gill Jennings & Every LLP represented Huawei in the filing.
Photonic interconnect technology
Traditional optical switches in AI systems face a key challenge: high signal quality often comes at the cost of complexity and expense, while simpler designs suffer from signal degradation. To address this, Huawei’s U.S. Patent No. 9,955,243 introduces a hybrid photonic interconnect architecture that balances performance and efficiency. By combining multiple types of optical switching components, the design delivers high cross-talk suppression with fewer parts and reduced cost—enabling ultra-fast, low-latency communication between densely packed processors in large-scale AI environments.
The invention also introduces a multi-stage switching method—referred to as a “jumpsuit switch” architecture—to manage data flow more efficiently. Instead of relying on a single hub, the system uses an intelligent first-stage switch to analyze incoming signals and route them across less-congested paths in a secondary stage, enabling real-time load balancing. This prevents bottlenecks before they occur, ensuring faster and more scalable network performance.
The patent, titled “Scalable silicon photonic switching architectures for optical networks” was filed on November 9, 2016, and was published on April 24,2018. Hamid Mehrvar is the inventor and was represented by Paul Hashim, Peter Meza, Ira Matsil, et al from Slater Matsil, LLP.
Network topology discovery via traffic similarity
Managing modern computer networks requires an accurate topological map but traditional network mapping methods are often slow, data-intensive, and struggle with compatibility across diverse hardware. Huawei addresses these challenges in U.S. Patent No. 10,361,923 with an intelligent, low-overhead approach to automated network discovery that relies only on basic traffic data.
Instead of extensive data collection, the system monitors data rates at each port. Ports with matching traffic patterns are assigned a “similarity score” to identify likely connections. A refinement process then resolves conflicts and confirms two-way links, producing a reliable network map with minimal data even in heterogeneous and complex environments.
The patent, titled “Method and device for discovering network topology” was filed on February 7, 2017, and was published on July 23,2019. H. Michael Hartmann, John Conklin, John Kilyk, et al from Leydig, Voit and Mayer Ltd represented Huawei in the patent filing. Yulin Yuan, Zhiming Ye, and Xiaoji Fan are listed as its inventors.
Network topology mapping and hierarchical layout
U.S. Patent No. 11,929,905 introduces a method for automatically generating clear and structured network maps by assigning a “network grade” to each device based on its role in the system. This grading process distinguishes core infrastructure (e.g., routers) from peripheral components (e.g., access switches), forming the foundation for a hierarchical network layout.
Once devices are graded, the method applies mathematical and geometric rules to place them in visually coherent positions. Core devices are positioned first, typically in a central circular formation or along a top axis, while other nodes are arranged in concentric layers or tree-like branches radiating from the center. This deterministic layout avoids crossed lines and visual clutter, resulting in symmetrical, easy-to-read diagrams that reflect the true structure of the network.
The patent, titled “Network topology determining method and apparatus, and system” was filed on June 3, 2021, and was published on March 12, 2024. Paul Hashim, Robert Hayden, Letao Qin, et al from Rimon PC represented Huawei in the patent filing. Hualin Huang, Zhenguang Chen, Bo Wang, Lu Yan, Yi Yang, and Yaojun Fu are listed as its inventors.
Network topology discovery through root-node probing
U.S. Patent No. 11,855,875 outlines a dynamic and automated method for discovering network topologies using an active messaging system.
The core mechanism involves a designated “root” device that sends probe messages through its ports. When a connected “child” device receives a message, it responds with its own port information, confirming a link. This iterative probing process extends through multiple layers of the network, allowing for the discovery of not just directly connected devices but also segments beyond the root’s immediate reach.
The patent, titled “Network topology discovery method and node device” was filed on April 28, 2022, and was published on December 26, 2023. Eric Hyman, Lester Vincent, et al from Womble Bond Dickinson LLP represented Huawei in the patent filing. Li Shen, Hanyu Wei, Yinliang Hu, Duoliang Fan, and Yunping Lyu are listed as its inventors.
Huawei’s path in AI hardware
Huawei’s approach to scaling AI chip production presents a complex picture of advancement alongside ongoing challenges. Innovations such as its CloudMatrix architecture, leveraging optical communication and 3D stacked memory designs, showcase a system-level focus that supports efficient, scalable AI performance, powered by the latest Ascend 910D chip.
While Huawei’s current solution uses more power and five times as many chips as comparable alternatives, it still meets a substantial share of China’s domestic AI computing needs. However, U.S. sanctions and manufacturing limitations continue to restrict production volumes, with delays in mass-producing the Ascend 910C highlighting these constraints.
Despite these setbacks, Huawei’s emphasis on system integration and its drive for technological self-reliance reinforce its role as a resilient force in China’s AI hardware landscape, even as it works to close the gap with global leaders.
